1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a method of designing thereof. In particular, the present invention relates to a power wiring structure of a semiconductor integrated circuit and a method of designing thereof.
2. Description of the Related Art
In general, a power wiring network of a semiconductor integrated circuit has a mesh wiring structure. Electric power supplied to a power pad is distributed to the mesh power wiring network through an I/O cell placed at a periphery of a semiconductor chip. A cell in the semiconductor integrated circuit receives a current from the power wiring network and consumes the current. Since the current is consumed at respective points in the semiconductor integrated circuit, a voltage drop (an IR drop) in the power wiring network increases towards the central part of the semiconductor chip, as shown in FIG. 1. In other words, the potential is high at the periphery of the semiconductor chip and decreases towards the central part of the semiconductor chip.
If the amount of the voltage drop exceeds an acceptable amount at a point, a cell placed at that point can not give its true performance sufficiently. In particular, since the potential becomes low around the central part of the chip, there is a possibility that malfunction such as decrease in an operation speed occurs at the cell placed in the vicinity of the central part. It is therefore desirable to provide a technique that can prevent the above-described malfunction caused by the voltage drop. Particularly in recent years, power supply potential is decreased and thus the influence of the voltage drop becomes conspicuous, with increasing miniaturization of the semiconductor integrated circuit. Measures for the voltage drop are one of the most important issues.
Japanese Laid-Open Patent Application JP-P2004-273844 describes a semiconductor integrated circuit. The semiconductor integrated circuit includes a first mesh power wiring for supplying predetermined power to a first region, and a second mesh power wiring for supplying the same power as the predetermined power to a second region which is different from the first region. The first mesh power wiring and the second mesh power wiring are separated from each other at a boundary between the first region and the second region. The first region is located at a periphery of a chip, and the power is directly supplied from a chip ring to the first mesh power wiring. On the other hand, the second region is located at a central part of the chip, and the power is supplied from the chip ring to the second mesh power wiring through a power supply wiring.